Data compression involves encoding information using fewer bits than the original data stream. Lempel-Ziv (LZ) compression algorithms, for example, achieve compression by replacing repeated occurrences of data with references to a single copy of the data existing earlier in the original data stream.
Data compression accelerators are often implemented in hardware to provide improved compression throughput and/or reduced power consumption. In existing data compression accelerators, area and logic resource requirements dictate the number of accelerators that may be incorporated onto a single chip.
A need exists for improved resource utilization by data compression accelerators, for example, in terms of reduced area and logic blocks.